1. Field of the Invention
The present invention relates to a data driving apparatus for organic electro luminescence display (OELD) panels, and more particularly to a data driving apparatus and method for driving an OELD panel that that improves a picture quality of the panel and while reducing the number of data drive switching devices used.
2. Description of the Related Art
Until recently, cathode ray tubes (CRTs) have generally been used in display systems. However, use of newly developed flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and electro-luminescence (EL) devices are becoming increasingly common due to their low weight, thin dimensions, and low power consumption.
PDPs, being thin, lightweight, and having large display areas, are structurally simple and relatively easy to manufacture. However, PDSs have relatively poor light emission characteristics causing the pictures they display to have a low brightness. Further, PDPs generally dissipate a large amount of power. Light emission characteristics of LCDs, on the other hand, are generally better than those of PDPs. However, LCDs having large display areas are difficult to fabricate LCDs because their manufacturing processes generally include those used in the semiconductor industry and are provided with a plurality of switching elements such as thin film transistors (TFTs). Accordingly, LCDs are generally used as display devices in notebook computers.
Depending on the type of material used as a light-emitting layer, EL devices are classifiable as inorganic EL devices or as organic EL devices. Generally, EL devices are self-luminous devices with excellent response speeds and light emission characteristics and are capable of displaying images at a high brightness and over wide ranges of viewing angles.
FIG. 1 illustrates a cross-sectional view of a related art organic electro-luminescence device.
Referring to FIG. 1, organic EL devices generally include a first electrode 14 made of a transparent, electrically conductive material, a hole injection layer 12 formed on the first electrode 14, a hole transport layer 10 formed on the hole injection layer 12, a light emission layer 8 formed on the hole transport layer 10, an electron transport layer 6 formed on the light emission layer 8, an electron injection layer 4 formed on the electron transport layer 6, and a second electrode 2, formed of a metallic material, is formed on the electron injection layer 4.
When a voltage is applied to the first and second electrodes 14 and 2, electrons generated at the second electrode 2 migrate toward the light emission layer 8 via the electron injection and transport layers 4 and 6, respectively, while holes generated at the first electrode 14 migrate toward the light emission layer 8 via the hole injection and transport layers 4 and 10, respectively. When the electrons recombine with the holes in the light emission layer 8, light is generated and emitted through the first electrode 14 to display pictures.
FIG. 2 illustrates a block diagram of a related art driving apparatus for driving an organic electro luminescence display panel.
Referring to FIG. 2, a related art driving apparatus is generally coupled to an OELD panel. The OELD panel includes an electro luminescence (EL) display panel 20 having pixel cells PE arranged at crossings of gate lines GL and data lines DL. The related art driving apparatus includes a scan driver 22 for driving the gate lines GL, a data driver 24 driving the data lines DL, and a controller 28 for controlling the driving of the scan and data drivers 22 and 24.
Gate signals applied from the gate lines GL enable pixel cells PE connected to the gate lines to generate light to a predetermined brightness according to a voltage associated with pixel signals applied from corresponding data lines DL.
The controller 28 simultaneously applies gate control signals GCS (i.e., start pulses and clock signals) to the scan driver 22 while applying data control signals and data signals to the data driver 24. In response to the gate control signals GCS applied from the controller 28, the scan driver 22 sequentially applies scan pulses SP to the gate lines GL. In response to the data control signals and data signals applied from the controller 28, the data driver 24 applies the data signals to the pixel cells PE via the data lines DL. Moreover, the data driver 24 applies the data signals to the data lines according to the application of the scan pulses SP to the gate lines GL by the scan driver 22 during each scan period.
FIG. 3 illustrates an equivalent circuit diagram of pixels within the organic electro luminescence display panel shown in FIG. 2.
Referring to FIG. 3, each of the pixel cells PE within the OELD panel 20 consist of an organic light emitting diode (OLED) connected to a cell drive voltage source VDD and a cell driver 26 for driving the OLED. The cell driver 26 is formed at crossings of each of the gate and data lines GL and DL and includes a first thin film transistor (TFT) T1 formed between the cell drive voltage source VDD and the OLED for driving the OLED; a second TFT T2 connected to the cell drive voltage source VDD to form a current mirror with the first TFT T1; a third TFT T3 connected between the second TFT T2, the data line DL, and the gate line GL, to respond to a signal applied from the gate line GL; a fourth TFT T4 connected between the gate terminals of the first TFT T1, the second TFT T2, the gate line GL, and the third TFT T3. Moreover, each pixel cell PE includes a storage capacitor Cst connected between the gate terminals of the first and second TFTs T1 and T2 and the cell drive voltage source VDD. The first to fourth TFTs T1 to T4 are generally provided as p-type MOS-FETs.
The third and fourth TFTs T3 and T4 each include source, drain, and gate terminals and may be turned on in response to a negative scan voltage applied from the gate lines GL, as shown in FIG. 4. When the third and fourth TFTs T3 and T4 are turned on (i.e., when the third and fourth TFTs T3 and T4 are maintained in an ON state), electrically conductive paths are created between the source and drain terminals third and fourth TFTs T3 and T4. When the voltage applied from the gate lines GL is less than a threshold voltage Vth of the third and fourth TFTs T3 and T4, the third and fourth TFTs T3 and T4 are turned off (i.e., third and fourth TFTs T3 and T4 are maintained in an OFF state) and the electrically conductive paths cease to exist. While the third and fourth TFTs T3 and T4 are maintained in the ON state, a data signal DATA applied from a corresponding one of the data lines DL is applied to the gate terminal of the first TFT T1 via the third and fourth TFTs T3 and T4. When the third and fourth TFTs T3 and T4 are maintained in the OFF state, a data signal DATA is not applied to the first TFT T1.
Accordingly, the first TFT T1 controls a current conducted between its source and drain terminals in accordance with the data signal DATA applied to its gate terminal to cause the OLED to emit light, wherein the brightness to which the light is emitted corresponds to the data signal DATA.
The second TFT T2 is provided as a current mirror of the first TFT T1 to uniformly control the current conducted from the first TFT T1 to the OLED.
The storage capacitor Cst stores a voltage equal to the voltage difference between the voltage associated with the data signal DATA and the cell drive voltage VDD. Accordingly, the capacitor Cst causes the voltage applied to the gate terminal of the first TFT T1 to be uniformly maintained during one frame period of the OLED while the current is uniformly applied to the OLED during the one frame period.
Upon driving the OELD panel 20 as shown in FIG. 4, a capacitance, having a magnitude dependent upon the structure of the OELD panel 20, in addition to a rising time of the data signal DATA applied to the data lines DL by the data driver 24, having an value dependent upon a line resistance, may increase. Such an increase in capacitance and rising time can distort the data signal DATA outputted by the data driver 24. As a result, the data signal DATA may not be sufficiently applied to a pixel cell PE during an enable period of the gate signal applied from the gate line GL and the quality at which pictures are displayable by the OELD panel 20 may be deteriorated. To prevent deterioration in the display quality, data signal controller circuits such as those shown in FIG. 5 can be electrically coupled to data lines DL of the related art OELD panel 20.
Referring to FIG. 5, related art data signal controller circuits are generally provided as a self-contained circuit set, separately formed from the related art OELD panel 20, and externally connectable to the data lines DL of the OELD panel 20. Moreover, the related art data signal controller circuits include a first data signal controller circuit 28A and a second data signal controller circuit 28B substantially identical to the first data signal controller circuit 28A. Lastly, the first and second data signal controller circuits 28A and 28B are connected in parallel between the data driver 24 and the data lines DL.
Accordingly, each of the first and second data signal controller circuits 28A and 28B include a first TFT S1 connected between the data driver 24 and a first node n1 arranged between the data line DL and a ground voltage source GND; a second TFT S2 forming a current mirror with the first TFT T1; a third TFT S3 connected between a second node n2, the first node n1, and the ground voltage source GND; a capacitor Cd connected between the second node n2 and the ground voltage source GND; and a fourth TFT S4 connected between the data line DL and the first node n1. Moreover, the first to fourth TFTs S1 to S4 are generally provided as n-type MOS-FETs.
First and second enable signals A and B, respectively, are alternately applied to gate terminals of the fourth TFTs S4 within the first and second data signal controller circuits 28A and 28B, allowing the first and second data signal controller circuits 28A and 28B to alternately sample a current and to alternately drive corresponding ones of the pixel cells PE. For example, the first data signal controller circuit 28A drives the pixel cells PE when the current is sampled by the second data signal controller circuit 28B.
Applied to the first TFTs S1 of the first and second data signal controller circuits 28A and 28B, first and second enable control signals A1 and B1, respectively, allow data signals DATA to be applied from the data driver 24 to the first node n1, and subsequently to the data line DL. As the first and second enable control signals A1 and B1 are applied to respective ones of the first TFTs S1, the first and second enable control signals A1 and B1 are simultaneously applied to the second TFTs S2 of the first and second data signal controller circuits 28A and 28B, allowing the second TFTs S2 to apply the data signal DATA to the second node n2.
The capacitor Cd is charged with a voltage associated with the data signal DATA applied to the second node n2 and applies the charged voltage to the gate terminal of the third TFT S3. As a result, the third TFT S3 can control the current between its source terminal and drain terminal in accordance with the data voltage charged in the capacitor Cd and transmit the controlled current to the pixel cells PE via the data line DL.
The fourth TFTs S4 of the first and second data signal controller circuits 28A and 28B are turned on in the presence of the applied first and second enable signals A and B. When turned on, the fourth TFTs S4 transmit the current outputted by corresponding ones of the third TFTs S3 to the data line DL.
FIG. 6 illustrates a waveform diagram of drive signals of the data signal controller circuit shown in FIG. 5.
Referring to FIG. 6, the first and second enable signals A and B are alternately applied to the fourth TFTs S4 of the first and second data signal controller circuits 28A and 28B. Accordingly, the first and second data signal controller circuits 28A and 28B are alternately driven over consecutive frames. First enable control signals A1, A2 and A3 applied to the first data signal controller circuit 28A cause a group of red, green, and blue data signals, respectively, to be inputted to corresponding ones of the data lines DL1, DL2, and DL3, respectively.
FIG. 7 illustrates an enlarged view of an exemplary portion of the related art data signal controller circuit shown in FIG. 5. FIG. 8A illustrates a first state of the exemplary portion of the related art data signal controller circuit shown in FIG. 7 while FIG. 8B illustrates a second state of the exemplary portion of the related art data signal controller circuit shown in FIG. 7.
Referring to FIGS. 7, 8A, and 8B, the related art data signal controller circuits include a plurality of shift registers 32 for shifting enable signals used to turn the first and second TFTs S1 and S2 on. Accordingly, data signal controller circuits have first and second states as shown below in TABLE 1.
TABLE 1First StateSecond StateS1ONOFFS2ONOFFS3OFFONStateCurrent is StoredCurrent is Applied to Pixel
Referring to FIG. 8A, the first and second TFTs S1 and S2 are maintained in an ON state, the fourth TFT T4 is maintained in an OFF state, and the related art data signal controller circuit is maintained in the first state. Accordingly, a current having a magnitude associated with the voltage of a data signal DATA applied from the data driver 24 is transmitted to the third TFT S3. As a result, the third TFT S3 acts as a diode while the capacitor Cd becomes charged with a voltage corresponding to the current transmitted to the third TFT S3.
Referring to FIG. 8B, the first and second TFTs S1 and S2 are turned off (i.e., maintained in their OFF states), the fourth TFT T4 is maintained in the ON state, and the related art data signal controller circuit is maintained in the second state. Accordingly, a current having a magnitude associated with the voltage stored by the capacitor Cd is transmitted by the third TFT S3 to the pixel cells PE via the data line DL.
Use of the related art data signal controller circuit described above, however, is disadvantageous because the first and second data signal controller circuits 28A and 28B are arranged in parallel. Accordingly, many switching devices must be used, thus complicating the operation and fabrication of the device.